Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC

This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by more than 20 dB with the proposed technique for a 14-bit SAR ADC

High-Resolution ADCs Design in Image Sensors

This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-ifications such as Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) in ultra-low power and high-resolution analog-to-digital converters (ADCs) including successive approximation register (SAR) for biomedical imaging application. The results show that with broad range of mismatch error, the SFDR is enhanced by about 10 dB with the proposed performance enhancement technique, which makes it suitable for high resolution image sensors sensing systems

High Linearity SAR ADC for Smart Sensor Applications

This paper presents capacitive array optimization technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor application. Monte Carlo simulation results show that capacitive array optimization technique proposed can make the SFDR, SNDR and (Signal-to-Noise Ratio) SNR more concentrated, which means the differences between maximum value and minimum value of SFDR, SNDR and SNR are much smaller than the conventional calibration techniques, more stable performance enhancement can be achieved, and the averaged SFDR is improved from 72.9 dB to 91.1 dB by using the capacitive array optimization method, 18.2 dB improvement of SFDR is obtained with only little expense of digital logic circuits, which makes it good choice for high resolution and high linearity smart sensing systems

The Design of Intelligent Sensor Interface Circuit Based on 1451.2

At present, there are many complex and diverse bus interface standards in the field of sensor measurement and control, which leads that different sensors unable to be compatible with different field networks, thus increasing the difficulty of data acquisition and processing. In order to improve the compatibility and the intelligent level of sensors, in this work, a novel intelligent sensor interface model defined by IEEE1451.2 standard is proposed. Finally, the self-recognition, plug and play (PNP) functions are verified on FPGA platform

The impact of government-enterprise collusion on environmental pollution in China

Pollution emissions in China are associated with the relationship between local governments and enterprises, especially in those cities with government-enterprise collusion (GEC). We evaluate the causal relationships between GEC and SO2 emissions at the enterprise level, by adopting the Propensity Score Matching–Difference in Difference method from a comprehensive environmental database. The empirical results show that, compared with those in the cities without collusion, SO2 emissions of enterprises in the colluded cities increase by 11.3% (95% Confidence Interval (CI): 0.041–0.186). These GEC effects are more substantial in the cities whose regional officials work with longer terms, in the foreign-owned or small-scale enterprises, and the labour-intensive industries. The findings suggest the existing environment and personnel management policies in China should be adjusted for more sustainable development.<br/

Study on Anti-Aging Performance Enhancement of Polymer Modified Asphalt with High Linear SBS Content

Modified asphalt with high content SBS is widely used in asphalt pavement due to its excellent high and low temperature performance. However, its anti-aging performance is insufficient. In order to improve the anti-aging performance of SBS modified asphalt, nano-ZnO, nano-TiO2, nano-SiO2 and polyphosphoric acid (PPA) were added to high content (6.5 wt%) linear SBS modified asphalt as anti-aging agents in this study. Moreover, Dynamic Shear Rheometer (DSR), Fluorescence Microscope, and Fourier Transform Infrared Spectroscopy were employed to reveal the mechanism, through the investigation of the rheological and microscopic properties of modified asphalt before and after aging. The results showed that the influence of nanoparticles on the rutting resistance and fatigue resistance of high content SBS modified asphalt is weak, mainly because there is only weak physical interaction between nanoparticles and the SBS modifier, but no obvious chemical reaction. The significant cross-networking structure of high content SBS modified asphalt even has an adverse effect on the anti-aging performance of nano-modifiers. However, PPA obviously makes the cross-linked network structure of SBS modified asphalt more compact, and significantly improves the performance after short-term aging and long-term aging, mainly due to the chemical reaction between PPA and the active groups in SBS modified asphalt

High Resolution and Linearity Enhanced SAR ADC for Wearable Sensing Systems

This paper presents linearity enhancement capacitor re-configuring technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of ADC simultaneously without sacrificing the sampling rate in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioural Monte-Carlo simulations are presented to demonstrate the effect of the proposed method where no complex least-mean-square (LMS) algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by about 18 dB and the SNDR is 15 dB better with the proposed technique for a 14-bit SAR ADC, which makes it suitable for accurate and linear smart sensor nodes in wearable sensing systems

Method for improving spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) of capacitor-resistor combined successive approximation register (SAR) analog-to-digital converter (ADC) by capacitor re-configuration

A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C1-C128; and 4) selecting 64 groups of capacitors from C33 to C96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter

Method for improving sfdr and sndr of capacitor-resistor combined sar adc by capacitor re-configuration

A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C1-C128; and 4) selecting 64 groups of capacitors from C33 to C96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter